1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a device having an element isolating region and a well region in such a device.
2. Description of the Prior Art
An element isolating method of the "groove isolation type", in which a groove is formed on the surface of the semiconductor substrate to embed an insulator therein, has conventionally been investigated in order to make a semiconductor device smaller and to enhance the reliability thereof. Examples of such a method are disclosed in Japanese Patent Laid-Open Nos. 124949/1985, 61430/1986 and 168241/1986.
In an element isolating region which is formed by such a conventional method, however, when a thermal oxide film is formed as in the process of forming a gate insulation film, the thickness of the oxide film becomes less at the upper corner of the groove than that at the flat portion, as shown in FIG. 6(a), which shows a semiconductor substrate 101 provided with an element isolating region 102, with a thermal oxide film 111 formed thereon. The reduced thickness region is circled. This unfavorable phenomenon is produced because the oxidation rate is lowered at a convex or concave portion of the silicon surface of the groove which is provided on the semiconductor substrate for forming an element isolating region 102 due to the stress concentration which is produced at the time of thermal oxidation. The smaller the curvature radius of the convex or concave portion is, the greater is the stress concentration and, hence, the greater is the degree to which the thermal oxide film at a concave or convex portion becomes thinner than that at the flat portion. Further, since an electric field concentration, due to the three dimensional configuration, is caused at the convex and the concave portions, the Fowler-Nordheim current greatly increases there, thereby deteriorating the insulating property of the oxide film. In element isolation, this phenomenon corresponds to the phenomenon which is produced when two transistors having gate insulation films of different thicknesses are connected in parallel. More specifically, referring to FIGS. 7(a) and 7(b), a hump is disadvantageously produced in Vgs-Ids characteristic 603 shown in FIG. 7(b) as the synthesis of the tail characteristics 601 and 602 of transistors shown in FIG. 7(a). In FIGS. 7(a) and 7(b), the reference numeral 601 shows the tail characteristic of a transistor formed at the flat portion, 602 the tail characteristic of a transistor formed at the corner portion, and 603 the combination of the tail characteristics of 601 and 602.
In order to eliminate these problems, Japanese Patent Laid-Open Nos. 45848/1988 and 276226/1986, for example, propose a rounding treatment of the convex and concave portions by thermal oxidation for mitigating the concentration of the electric field there. As is known, if a gate insulation film is formed after this treatment, it is possible to obtain a gate insulation film having a more uniform thickness, such as that shown in FIG. 6(b).
In other words, it is now common knowledge that this technique is required in order to put an element isolating region of a groove isolation type to practical use.
Accordingly, a method of manufacturing a semiconductor device is composed of the steps of forming a well region, implanting a channel stopper in a groove, rounding the convex and concave portions, embedding an insulator in the groove and forming a transistor and wiring. For example, a known semiconductor device is manufactured in such a manner as shown in FIGS. 5(a) to 5(g), by carrying out the following steps in the order listed:
1. P Well photolithography PA0 2. P Well ion implantation PA0 3. N Well photolithography PA0 4. N Well Ion implantation PA0 5. Drive in (activation) PA0 6. SiO.sub.2 deposition PA0 7. Photolithography for groove isolation PA0 8. SiO.sub.2 etching PA0 9. Etching for groove isolation PA0 10. Channel stopper photolithography PA0 11. Channel stopper ion isolation PA0 12. Rounding oxide treatment PA0 13. SiO.sub.2 deposition PA0 14. SiO.sub.2 etching PA0 15. Gate insulation film forming
More specifically, a method of manufacturing a semiconductor device having a CMOS structure will be explained.
In FIGS. 5, a semiconductor substrate 101 consisting of N-type silicon or the like, is to be provided with an element isolating region 102, a P well 105, a channel stopper 112, an N well 115, photoresist layers 116a-d, phosphorus (P) doping 118 and boron (B) doping 120, with the aid of ion beams 117 and 119, thermal oxide films 121a and b, and a CVD oxide film 122.
The wells 105 and 115 are first formed in order to form P and N channels, respectively (FIGS. 5(a) to 5(c)). The wells are formed to a depth of several .mu.m by thermal treatment. Phosphorus doping 118 and boron doping 120 are effected by ion implantation and wells 105 and 115 are then formed.
On the semiconductor substrate 101 with the wells 105 and 115 formed thereon, the CVD oxide film 122, such as a silicon oxide film, is formed. The semiconductor substrate 101 and the CVD oxide film 122 are etched to form grooves while using the photoresist 116c as a mask (FIG. 5(d)). Etching of the CVD oxide film 122 is necessary for forming the channel stoppers 112 only in the grooves at the next step.
The channel stoppers 112 are then formed in the grooves of the P well 105 by ion implantation using the CVD oxide film 122 and a new photoresist layer 116d as a mask.
Thereafter, the photoresist layer 116d and the CVD oxide film 122 are removed by etching (FIGS. 5(e) to 5(f)). As a rounding treatment, the semiconductor substrate is oxidized to a depth of 1500 .ANG. at a temperature of 1150.degree. C. in a 10% oxygen atmosphere. The P well 105 becomes 1.5 to 2 times deeper by this heat treatment.
A new CVD silicon oxide film is then formed and etched back so as to form element isolating regions 102 with the insulator embedded therein (FIG. 5(g)).
A transistor, wiring, and a protective film are then formed, if necessary, thereby completing the semiconductor device. FIG. 4 shows one embodiment of a semiconductor device produced on the structure of FIG. 5(g). In FIG. 4, the reference numerals indicate the same elements as in FIGS. 1, 5 and 6.
The above-described conventional technique, however, has the following problems.
After the grooves are formed, the substrate is oxidized to a thickness of not less than 1500 .ANG. at a temperature of 1150.degree. C. in an oxygen atmosphere so as to round the upper corners of the grooves and prevent the deterioration of the element characteristics such as deterioration of the gate breakdown characteristics and hump of the tail characteristic which are caused by the concentration of electric field on the corners of the gate ends of the semiconductor device.
At this time, since the impurity density of the surface of the semiconductor substrate is lowered by the oxidation, because the portion of the surface of the substrate of silicon or the like at which the density of the impurities is high becomes an oxide, the threshold voltages of the field (parasitic) MOS transistors (FIG. 4: 130, 140 and 150) which are formed in the element isolating regions are lowered too much to obtain a sufficient capacitance. Especially, the surface density of the field MOS transistor 150 under the element isolating region of the P well is lowered, so that a current leakage is produced between the wells by the inversion of the field. This phenomenon is produced when boron, which is an impurity, is mixed with the oxide film during the oxidation. The threshold voltage of the field MOS transistor which is formed in the element isolating region is generally raised by forming a channel stopper in the groove of the P well by implanting boron ions only in the groove. In this case, however, since the channel stopper is diffused to the surface of the substrate, the threshold voltage of the transistor in the element forming region is disadvantageously raised. Since this phenomenon is prominent at the boundary of the element isolating region and the surface of the substrate, the threshold voltage of the transistor is undesirably dependent on the width of the channel. This result is generally called a narrow channel effect, which deteriorates the characteristics of the element.
Since it is impossible to reduce the depth of the well, the channel stopper also is diffused in the transverse direction, so that almost double the distance between the wells is required.